1. Field of the Invention
The present invention relates to a terminal structure, and a semiconductor element and a module substrate comprising the same.
2. Related Background Art
In cases where an advanced semiconductor, such as a CPU (Central Processing Unit), is densely packaged, the transition proceeds from a packaging method using bonding wires, which is a general-purpose technique, to a flip chip packaging method in which bumps comprising solder and the like are formed on chip electrodes at a narrow pitch and directly bonded to a substrate. For example, methods for forming bumps on electrodes provided on a base material are disclosed in Patent Literature 1 (Japanese Patent Application Laid-Open No. 2001-085456) and Patent Literature 2 (Japanese Patent Application Laid-Open No. 2002-203868).
A general method for forming bumps on electrodes is shown in FIG. 1. In this method, first, as shown in FIG. 1(a), a substrate in which external electrodes 20, a passivation layer (insulating covering layer) 30, and a seed layer 40 are formed on a base material 10 is prepared. Next, a dry film 100 is formed so as to cover part of the seed layer, and electrolytic plating is performed in the order of electrolytic nickel plating and electrolytic solder plating to form under bump metal layers 50 and solder plating layers 60 (FIG. 1(b)). Then, the dry film is peeled, and the unnecessary seed layer is removed by etching (FIG. 1(c)). Then, by placing the entire substrate in a reflow furnace and heating it, bumps 65 are formed (FIG. 1(d)).